In present semiconductor technology, CMOS devices, such as nFETs or pFETs, are typically fabricated upon semiconductor wafers, such as Si, that have a single crystal orientation. In particular, most of today's semiconductor devices are built upon Si having a (100) crystal orientation.
On one hand, electrons are known to have a high mobility for a (100) Si surface orientation, but holes are known to have a high mobility for a (110) surface orientation. That is, hole mobility values on (100) Si are roughly 2×-4× lower than the corresponding electron mobility for this crystallographic orientation. To compensate for this discrepancy, pFETs are typically designed with larger widths in order to balance pull-up currents against the nFET pull-down currents and achieve uniform circuit switching. pFETs having larger widths are undesirable since they take up a significant amount of chip area, and add capacitance, resulting in increased circuit delay and power.
On the other hand, hole mobility on (110) Si is 2× higher than on (100) Si; therefore, pFETs formed on a (110) surface will exhibit significantly higher drive currents than pFETs formed on a (100) surface. Unfortunately, electron mobility on (110) Si surfaces is significantly degraded compared to (100) Si surfaces.
As can be deduced from the above, the (110) Si surface is optimal for pFET devices because of excellent hole mobility, yet such a crystal orientation is completely inappropriate for nFET devices. Instead, the (100) Si surface is optimal for nFET devices since that crystal orientation favors electron mobility.
Hybrid orientation substrates having planar surfaces with different crystallographic orientation have recently been developed. See, for example, U.S. patent application Ser. No. 10/250,241, filed Jun. 23, 2003 and U.S. patent application Ser. No. 10/696,634, filed Oct. 29, 2003, the entire contents of each of the aforementioned U.S. Patent Applications are incorporated herein by reference. Additionally, hybrid-orientated metal oxide semiconductor field effect transistors (MOSFETs) have recently demonstrated significantly higher circuit performance at the 90 nm technology node. As discussed above, the electron mobility and hole mobility can be optimized independently by placing the nFET on a (100) surface and the pFET on a (110) surface.
In some versions of prior art hybrid orientation substrates, the HOT substrate provided includes a bulk-like region having an upper surface of a first crystallographic orientation and an SOI region having an upper surface of a second crystallographic orientation, wherein said second crystallographic orientation differs from said first. Such a structure is shown in FIG. 1 wherein reference numeral 10 denotes a lower semiconductor layer of a first crystallographic orientation, reference numeral 12 denotes a buried insulating layer, reference numeral 14 denotes an upper semiconductor layer of a second crystallographic orientation, which differs from said first, and reference numeral 16 denotes an epitaxially grown semiconductor layer. Reference numeral 18 denotes isolation regions that are used in separating the bulk-like regions from the SOI regions. The terms “bulk-like” and “SOI” are shown in the drawing to illustrate these different regions of the hybrid orientation substrate.
In such a hybrid orientation substrate, the pFETs are typically formed on the bulk-like regions, while the nFETs are formed on the SOI regions. It is also possible to reverse this situation, placing the pFETs in SOI regions, while placing the nFETs in bulk-like regions. In the following descriptions, the former case is described; however, it would be clear to one skilled in the state-of-the-art that this description is easily extended to include the later case, simply exchanging n-type and p-type regions (e.g., n-wells are replaced by p-wells).
Porting of SOI designs into hybrid orientation substrates requires extensive design modifications to add n-well contacts for pFETs. Such design modifications are disadvantageous because they tend to be costly and add extra time to the overall design manufacturing process.
Moreover, many of the prior art techniques that add n-well contacts to a hybrid orientation substrate incur limitations to effective suppression of electrical noise coupling among transistors via the n-well which can result in unsatisfactory operation of the CMOS circuits.
In view of the above, a technique is needed that can add wells and well contacts of a second conductivity type for FETs of a first conductivity type in a hybrid orientation substrate of the kind illustrated in FIG. 1 wherein the well contact provides a large capacitance from a well region to the underlying substrate thereby providing noise decoupling with fewer well contacts than what is typically used in prior art buried well designs. In particular, there is a need for providing an n-well contact for pFETs.